The present disclosure relates in general to the field of computer systems, and, more particularly, to a system and method for handling numerous power management signals in a multiple-peer bus computer environment.
The peripheral component interconnect (PCI) local bus standard is implemented in most computer systems, along with the more general industry standard architecture (ISA) expansion bus. Generally, PCI is a 32-bit or 64-bit bus and can run at clock speeds of 33 or 66 MHz. The PCI bus provides a mechanism to allow a device to wake or turn on the computer system containing the PCI bus while the computer system is powered-down or in a sleep state. The PCI bus implements this mechanism through a power management signal such as a power management event (PME#) signal. Any computer component or device may assert a power management signal to request that the computer system power up. For example, an outside system may attempt to access a local computer system that has powered down. The network card of the powered down local computer system may wake the local computer system in response to the outside system""s attempts to access the local computer system. Another example may be one in which a system component detects an imminent failure and wakes the powered down computer system to prevent the loss of data.
Typically, the power management signal is transmitted to the south bridge, super I/O, or other computer component operable to control the power state of the computer system. Upon the assertion of the power management signal, the south bridge or super I/O will power up the computer system and record in one of the registers associated with the south bridge or super I/O the reason for the power up or wake-up event. The operating system (OS) for the computer system may utilize a power management specification such as the advanced configuration and power interface (ACPI) specification. ACPI enables the OS to control the amount of power delivered to each device coupled to the computer system. With ACPI, the OS can turn off peripheral devices that are not in use. Alternatively, ACPI may be used to power up the computer system upon receipt of a signal from a peripheral device. If the OS utilizes ACPI or a similar power management specification, the OS can access this register to determine the that the cause of the power-up was the assertion of a power management signal. The OS may then scan the PCI buses to determine which device or devices asserted the power management signal. Once the PCI devices have been identified, the OS can acknowledge the power management signal and the PCI device will cease asserting the power management signal.
The PCI buses are preferably configured in a peer bus arrangement rather than a hierarchical arrangement. In a hierarchical arrangement, one bus is connected to the north bridge, or other device that serves as the primary interconnect between major system components. The other buses are connected to the north bridge through this primary bus. A hierarchical arrangement is typically implemented due to hardware constraints that prevent coupling several devices to a single bus or single bus type. In contrast, in a peer bus arrangement, each bus is directly connected to the north bridge. As a result, the peer buses have a higher throughput than hierarchical buses.
However, several leading OSs require a dedicated power management signal input for each peer bus in order for the OS to successfully determine from which bus a wake-up event was requested. Therefore, if the computer system contains four peer buses that are operable to transmit power management signals, then the chip set must contain four dedicated power management signal inputs. The dedicated power management signal inputs are operable to initiate a power-up and record the wake-up event in a register that may be accessed by the OS. If the computer system does not implement a dedicated power management signal input for each peer bus, then an OS deadlock condition may occur when the OS attempts to acknowledge the transmission of a power management signal. For example, if the OS scans a bus that did not in fact communicate a power management signal, the OS may become caught in an infinite loop as it repetitively scans the incorrect bus in an attempt to determine which PCI device or card had asserted the power management signal. As long as each peer bus has a dedicated power management signal input that will receive power management signals from that peer bus, this type of OS deadlock can be avoided.
Unfortunately, conventional chip sets only provide a limited number of power management signal inputs. For example, many conventional chip sets only provide up to four dedicated power management signal inputs. This limitation is highlighted by the trend in computer system design to increase the number of peer buses installed in a computer system in order to accommodate a larger number of PCI devices. As a result, OS deadlock conditions are a concern for computer systems that contain a large number of peer buses and run one of many leading OSs which require dedicated power management signal inputs. In order to avoid the risk of OS deadlock, power management signaling must be limited such that only a few peer buses are capable of waking the computer system. For example, if the chip set only provides two dedicated power management signal inputs, then the computer system is limited to having only two peer buses that are operable to wake the computer system. Thus, conventional power management signaling methods are inadequate for computer systems that are running certain types of OSs and are intended to couple with a large number of PCI devices.
In accordance with teachings of the present disclosure, a system and method for communicating multiple power management signals to an I/O interface component of a computer system are disclosed that provide significant advantages over prior developed systems.
The system and method of the present invention utilizes a logic circuit to logically OR the power management signals from the PCI buses and couple the output signal to the dedicated power management signal input on the south bridge, super I/O or other power state management device. This configuration allows any power management signal sent by a PCI device to issue a power up request to the computer system. Because the power management signal may be negatively asserted, such as a PME# signal for example, the logical OR function may be accomplished by an AND logic gate. In addition, each power management signal is also coupled to an individual general purpose input on the south bridge, super I/O, or other power state management device. Each general purpose input can store the status from its respective power management signal.
When a PCI device asserts a power management signal, the OR logic will transmit the signal to the dedicated power management signal input and thereby issue a power-up request to the computer system. The power management signal assertion is recorded by the dedicated general purpose input for that particular PCI bus. After the computer system boots, the BIOS checks the power state management device to determine whether the computer system powered up as a result of a power management signal assertion, and if so, checks which power management signal general purpose input or inputs were tripped. The BIOS makes available to the OS the locations or addresses of the general purpose inputs that store the status from each asserted power management signal. By reading the general purpose inputs at these addresses, the OS can identify the bus or buses on which a PCI device is asserting a power management signal. The OS can then search the correct bus or buses and locate the PCI devices that are asserting the power management signals.
Alternatively, instead of reporting the availability of the power management signal input to the OS, the BIOS creates and makes available to the OS a virtualized power management signal input or a memory location corresponding to the general purpose input so that the OS can identify from which bus the power management signal is being asserted. The OS checks this virtualized power management signal input or memory location and subsequently determines on which bus or buses resided the device or devices that asserted the power management signal. The OS can then search the correct bus or buses and locate the PCI devices that are asserting power management signals.
A technical advantage of the present invention is that the power management signals are tied together as one signal that may be transmitted to a single dedicated power management signal input in the power state management device. Because the power management signal input is virtualized, the OS can still determine on which bus resided the device that asserted the power management signal. As a result, the number of PCI devices that may be coupled to the computer systems is not limited by the number of dedicated power management signal inputs in the power state management device. Thus, the computer system may be coupled to several PCI devices without the risk of an OS deadlock condition. Another advantage of the present invention is that it may be implemented with currently available components. It is not necessary to modify the south bridge or super I/O because only one power management signal input is required.
Other technical advantages should be apparent to one of ordinary skill in the art in view of the specification, claims, and drawings.